What is PSoC
A programmable system on a chip (SoC) is defined differently depending on its use. One definition is an FPGA that is so huge and has so many logic gates that it replaces a complete system that, only a few years ago, would have required an entire board full of chips. A microprocessor is required in a programmable SoC in the meaning of this article. As a result, any FPGA that incorporates a microprocessor and is both hardware and software programmable is a programmable SoC.
Introduction of FPSoC
An FPGA is a programmable SoC if it has enough gates to enable a microprocessor architecture and includes enough gates to support it. These two terms refer to the two types of processors found in programmable SoCs: hard and soft processors. A third form of programmable SoC is one that has numerous CPU and peripheral components that may be attached or detached programmatically. This varies from a F)GA-based programmable SoC in that the programmability is at a very high level of functionality, limiting the ability to construct low-level, user-defined functionalities on a device.
Advantages of FPSoC
FPSoCs provide a number of advantages. Let’s begin with some of the most important benefits.
FPGAs are high-performance parallel processors. An FPGA can run an application very efficiently if it can be parallelized. FPGA fabric acceleration is a suitable fit for applications like Hadoop, LTE/5G channel scheduling, speech recognition and deep packet inspection. For 2 applications, Hadoop MapReduce and sorting, the performance of an FPGA-based implementation is compared to that of a completely software-based version. When compared to best-in-class SoCs, the authors discovered that application acceleration using the FPGA resulted in 10x and 20x performance enhancements, respectively.
Bridging Devices and Glue Logic
Synchronous interfaces (either a LVDS/subLVDS source or RGB (LVCMOS) parallel bus) provided camera and display interfaces traditionally. On the other hand, traditional interfaces are rapidly giving way to MIPI-based alternatives. The issue is that not all display interfaces or camera has migrated to the MPHY or MIPI DPHY standards. And hence not all mobile SoCs have done so. This necessitates the use of a bridge device to link old and new interfaces. An FPGA is frequently used as a bridge device. FPGA fabric is already incorporated in the SoC in an FPSoC, and it may be utilized to execute the bridging function.
On a CPU, the time it takes for a function to run varies from one run to the next. Interrupts, system calls, cache misses, and bus congestion, to mention a few, all contribute to the unpredictability in the run time. This unpredictability is a cause of worry in applications that demand predictable latency, such as L2 network scheduling. However, there would be no variability or jitter if the identical function were implemented on an FPGA. FPGAs are pre-programmed, deterministic devices.
When compared to their rivals’ products, OEMs personalize their solutions to create difference and additional value. OEMs may tweak both the software and the hardware with FPSoC devices. Customers may, for example, want to alter how incoming and outgoing traffic is scheduled and queued according on the application’s needs. Change the queue structure and scheduling algorithms in RTL without losing performance or functionality using a Hybrid SoC-FPGA device. Parsing and Traffic categorization are another examples, which may be tailored to the customer’s specifications in the FPGA without losing speed. It’s worth noting that customisation may also be accomplished by altering the software to implement the new functionality on the CPU, but this technique always results in a performance impact.
Protection Against Evolving Specifications
Standards change at a quicker rate than SoCs can keep up with. System architects frequently employ separate FPGA devices to adapt changes in the specification in order to maintain their systems compliant and interoperable. Designers may not require the additional FPGA device with an FPSoC device system since the integrated FGPA fabric can be configured to handle any incompatibilities, lowering the system’s cost.
Lower Frequency and Lower Power Consumption
As formerly stated, FPGAs are designed to be parallel machines with huge information channels; as a result, in comparison to a CPU middle or different hardware accelerator, the FPGA material might also additionally run at a decrease frequency even as nevertheless assembly information price necessities. We recognise that electricity is associated with frequency, consequently decreasing the frequency lowers electricity usage. Different sorting algorithms had been advanced on one FPGA and severa SoCs in a single study. When an FPGA become hired in place of a SoC, the findings discovered a 2.5-fold electricity savings. This electricity advantage become because of the FPGA’s decreased frequency necessities in comparison to the SoC.
Challenges of the FPSoC
In comparison to ASICs/ASSPs and SoCs, FPGA fabrics consume a lot of power. A single LUT is roughly comparable to 6 to 10 ASIC gates, according to the rule of thumb. The overall power consumption may be increased by embedding the FPGA fabric. This increase in power must be reduced by the 2 factors. The first factor is trimming the fabric routing as previously described. And the second factor is employing suitable power management strategies such as putting the fabric to sleep or deep sleep with or without state retention during non-active times. During my time at Lattice Semiconductor as Director of Architecture and Systems, I pioneered power management techniques in FPGAs, where they had previously been unavailable (not just at Lattice, but across the whole FPGA industry).
The FPGA fabric’s size would be determined by the amount of application acceleration necessary. If the desired application space isn’t tight enough, establishing the size of the FPGA fabric required becomes difficult.
Another significant problem is integrating programming and debugging tools. The success of such a gadget depends on the proper integration of tools. System developers should be able to go from writing C code to RTL (or C-like-RTL) code without difficulty. Configuring and programming the device should not demand two independent skill sets from system developers. The tools should also assist in establishing the best way to split work across CPUs, hardware accelerators, and the FPGA fabric.
FPGAs (Field Programmable Gate Arrays) are programmable devices. To setup the FPGA fabric, they need a boot program called a “bit stream.” The RTL function is implemented by the FPGA fabric when it has been setup. FPGA setup, on the other hand, takes a lengthy time. It may take several milliseconds depending on the size of the cloth. If the FPGA fabric is only configured at startup time, this configuration time may be acceptable. However it is not allowable if runtime reconfiguring is necessary.
All current systems must have the capacity to execute a secure boot. The bit stream would be put into the gadget in the same manner it does currently in the case of embedded FGPA fabric. The only distinction is it will be packaged with the SoC’s boot code. If variable reconfiguration is needed, or if the bit stream has to be changed in the field, it would be done in the same safe way that application code is updated today. However, the development of the suitable protocol or sequence for changing the configuration of the integrated FPGA fabric must be carefully considered.