Among the electronic equipment chips currently on the market, the most advanced is still the 7nm EUV process, which is used in mobile phone chips from mobile phone manufacturers such as Apple and Huawei.
With the upcoming launch of chips using 5nm process technology in February of this year, 5nm process chips are expected to dominate the high-end chip market this year and next.
According to a report in “Korea Economics” magazine, Samsung Electronics has successfully developed the first 3nm process chip based on all-gate (GAAFET) technology.
Compared with the 5nm chip developed by Samsung using the FinFET process, the total silicon area of the 3nm chip is reduced by 35%, the power consumption is reduced by 50%, and the performance is improved by 30%.
At the end of December last year, Samsung Electronics planned to invest US$116 billion to upgrade the chip industry and invest in semiconductor miniaturization, a process called extreme ultraviolet lithography (EUV). This is the most expensive manufacturing upgrade Samsung has tried so far.
Samsung Electronics’ GAAFET process
As early as a year ago, Samsung began research and development of the 3nm GAAFET process, and initially planned to start mass production in 2021.
At the same time, Samsung has also stated that it will adopt the 4nm GAAFET process before 2020, but the industry doubts whether Samsung can mass produce the process before 2020.
In fact, Samsung put the GAAFET chip into production earlier than the industry expected. But with the development of Samsung’s 3nm chip prototype, its mass production time may be earlier than market expectations.
In fact, the process design of GAAFET is quite different from FinFET.
The FinFET process designs the gate into a 3D structure like a fish fin. Turning the internal structure of the chip that was previously horizontal to vertical and thinning the thickness of the crystal.
This design can not only turn on and off the current on both sides of the circuit well, greatly reduce the problem of high leakage rate of the chip, but also greatly shorten the gate length between the transistors.
The GAAFET process is designed around the four sides of the channel to ensure that the leakage of power is reduced and the control of the channel is further improved.
In addition, the GAAFET process can also achieve more efficient transistor design, has a smaller overall process size, and greatly improves the performance per watt of the chip.
Development and commercialization of the 3nm process
At the end of 2016, TSMC announced plans to build a 5 nm to 3 nm node wafer fabrication plant, with a committed investment of approximately US$15.7 billion.
TSMC announced in 2017 that it has begun building a 3nm semiconductor manufacturing plant in Tainan Science Park, Taiwan, and plans to start mass production of 3nm process chips in 2023.
In 2018, IMEC and Cadence announced the use of extreme ultraviolet lithography (EUV) and 193 nm immersion lithography technology to successfully tape out 3 nm test chips.
Early 2019, Samsung proposed to use its self-developed nanochip (not nanowire nanowire) MBCFET transistor structure technology to manufacture 3 nm chips in 2021.
Compared with 7nm, this chip performance can be improved by 35%, power consumption can be reduced by 50%, and area can be reduced by 45%.
In December 2019, Intel announced plans to mass produce 3-nanometer chips in 2025, and plans to produce 1.4 nm in 2029.
Samsung announced in January 2020 the development of the world’s first 3nm GAAFET process prototype, and it will achieve mass production in 2021.
TSMC announced the details of its N3 3 nm process in August 2020. This is a new process with significant improvements, not an iterative upgrade to the N5 5 nm process.
Compared with N5, N3 can increase performance by 10-15%. It reduces power consumption by 25-35%, and increase logic density by 1.7 times. TSMC plans to carry out risk production in 2021 and achieve mass production in the second half of 2022.
In May 2021, IBM announced the development of 2 nm chip manufacturing technology. They successfully manufactured a “nail size” chip prototype with more than 50 billion transistors.
Samsung has used GAAFET technology to create SRAM chips
Last year, Samsung announced that they had overcome the key technology of 3nm process GAAFET process. It is expected to officially launch this process in 2022. There is little news about this process at present.
Tomshardware reported that Samsung has integrated in IEEE International. At the circuit conference, Samsung announced some details of the 3GAE process.
There are actually two types of GAAFETs, one is a common GAAFET that uses nanowires as electronic transistor fins. The other is a multi-bridge channel field effect electronic transistor MBCFET with thicker fins in the form of nanosheets.
Both of them surround the channel region on the side where the gate material is located. The realization of nanowires and nanosheets depends largely on the design. Generally speaking, GAAFETs are used to describe both.
GAAFET actually appeared as early as 1988. This transistor allows designers to precisely tune it by adjusting the width of the transistor channel to achieve high performance. Wider flakes can achieve higher performance at higher power.
When implementing similar designs on FinFETs, engineers must use additional fins to improve performance. But in this case, the “width” of the transistor channel can only be doubled or doubled. The accuracy is not very good.
Advantage of GAAFET
Samsung said that compared with the 7LPP process, the 3GAE process can increase performance by 30% at the same power consumption. It also reduces power consumption by 50% at the same frequency, and increase transistor density by up to 80%.
Samsung demonstrated the first SRAM chip using MBCFET technology. The area of this 256Gb chip is 56mm2. Compared with the existing chip, the write voltage of this MBCFET technology is reduced by 230mV. It can be seen that MBCFET can indeed reduce power consumption.
SRAM is actually a relatively simple chip. At present, Samsung has not seen the ability to use this technology to produce duplicate chips. I believe that Samsung can solve this problem in some time. It is expected that the 3nm MBCFET process will be put into production in 2022.
TSMC is still making efforts in the 5nm field
Samsung Electronics’ old rival, TSMC, seems to be relatively low-key in the 3nm process field.
TSMC has stated that it will start the construction of 3nm wafer fabs at the end of 2019.
On the contrary, TSMC is now focusing more on the development of the 5nm process.
Last year, TSMC’s first batch of 5nm processes has successfully won Apple and Huawei HiSilicon’s two major customers.
According to the latest news, the average yield of TSMC 5nm process has increased to 50%. We can see mass production in the first half of 2020.
Samsung Electronics stated that its goal is to become the world’s number one semiconductor manufacturer by 2030.
Conclusion: Wars in the field of advanced chip manufacturing
TSMC and Samsung’s chip foundry battle has intensified, especially in the field of advanced manufacturing processes of 5nm and below.
In addition to the dispute over yield, performance and customer orders, the two sides have focused on chip technology. The competition is also more intense.
Although Samsung has announced the latest progress of its 3nm process. TSMC is still superior in terms of yield and orders. In the future, can Samsung, which lost 7nm, win back a city at 3nm? We will wait and see.